• National Palace Museum
  • Grand Hotel
  • Taipei-101
  • Jade Mountain












Keynote Speakers


Dr. Alek C. Chen

  • Director, Technology Development Center - Asia ASML
    Title : EUVL, the future lithographic technology for semiconductor fabrication

  • Abstract
    The lithographic process is a crucial fabrication process for all semiconductor devices. The current lithography process has to rely on multiple patterning steps as the semiconductor device scaling down to 30nm half-pitch (HP) and below. This presents a significant cost increase as the device geometry continues to decrease as described by the Moore’s law, a doubling of device per unit area in every two years. EUV (Extreme Ultra Violet) lithography is believe to be the most cost effective method for semiconductor device scaling down to below 20nm half-pitch (HP). A brief introduction of lithographic process and equipment will be presented. Then the challenges and current status of EUVL will be provided in detail. Finally, the future direction of lithography, in general, and EUVL particularly will be given.
  • Biography
    Alek C. Chen, Ph.D. has been the current position at ASML since 2001 with the responsibility of collaborative R&D in lithography technology with Asian customers and partners. The area of research involves the patterning process control, metrology, low k1 imaging, ArF immersion and EUV lithography.

    Currently he serves on the programming committee of SPIE Process Control and Metrology conference, steering committee of Microprocesses and Nano-technology conference. He also served as the conference chair of SPIE-Asia conferences in 2008 and 2009. He published extensively and held several patents all in lithography related area.

    Before joining ASML, Alek held various management and technical positions at IBM. During his 19 years at IBM, he worked in the area of lithography R&D for proximity X-ray, DUV and ArF technology, as well as in the process development for advanced logic and memory products.

    Alek received his Ph.D. and M.S. from the University of Illinois at Urbana-Champaign IL, USA, and B.S. from the Columbia University in the City of New York, NY, USA. He is a member of SPIE, and IEEE.


Toshiaki Tsuchiya, IEEE Fellow

  • Interdisciplinary Graduate School of Science and Engineering,
    Shimane University

  • Title: Detection of Single Traps and Characterization of Individual Traps: Beginning of “Atomistic Reliability Physics”

  • Abstract
    Trap centers are attributed to the so-called “defects”, and it will be almost impossible to eliminate them completely even in future atomistic devices. Such traps will cause wrong operations and reliability problems in these devices. Therefore, it is considered that studies on trap physics will become increasingly important. In this paper, our recent works on detection of single traps and characterization of individual traps are reviewed. The charge pumping (CP) technique is known to be the only highly-precise and powerful method for evaluating the density of interface traps even in extremely small-area MOSFETs, therefore, the method has been widely used for the last 30 years. We made systematic measurements of the maximum CP current (ICPMAX) from single Si/SiO2 interface traps, and successfully observed for the first time that their current range is 0<ICPMAX≤2fq (f: the gate pulse frequency, q: the electron charge). This range can be expected from the nature of the Pb0 centers, in other words, we succeeded to directly and electrically observe the Pb0 centers. We show that the conventional belief in the CP theory, i.e., ICPMAX is given by fqN (N: the total number of traps contributing to the CP current), is basically wrong, and we demonstrate fundamental trap-counting by the CP method. Moreover, we show direct observation of the elementary processes concerning the interaction between individual interface traps in the capture/emission processes. Furthermore, we show characterization of individual oxide traps that participate multi-trap random telegraph noise (RTN) in nanoscale MOSFETs, by applying a novel method developed using “charging history effects” on the traps. It is quite difficult to characterize the individual traps using the conventional method.
  • Biography
        Toshiaki Tsuchiya received the B.S., M.S., and Ph.D. degrees in electrical engineering from Waseda University, Tokyo, Japan, in 1974, 1976, and 1988, respectively.

        In 1976, he joined the Electrical Communication Laboratories, Nippon Telegraph and Telephone Public Corporation (now NTT), Tokyo, Japan. Since then, he has been engaged in research on physics, design, and process technologies of advanced scaled-down CMOS devices, such as low-voltage/low-power/high-speed thin-film FD-CMOS/SOI and MTCMOS (Multi-Threshold CMOS)/SOI using SIMOX technology, hot-carrier effects and reliability physics in CMOS devices, radiation-hard devices, dynamic MOS memory devices including gain memory cells, and so on. From 1983 to 1984, he was a Visiting Fellow at the School of Electrical Engineering, Cornell University, Ithaca, NY, USA. From 1998, He has been a professor of the Interdisciplinary Graduate School of Science and Engineering, Shimane University, Shimane, Japan. In the university, he has studied nanoscale CMOS devices, SiGe/Si heterostructure MOS devices, and low-temperature poly-Si thin-film-transistors, focusing on the reliability physics of these devices. He is now concentrating his efforts on characterization of individual traps by analyzing charge pumping phenomena and random telegraph noise in nanoscale MOSFETs, aiming to construct “Atomistic Reliability Physics”. He has authored or coauthored seven books and over 160 technical papers.

        Dr. Tsuchiya has been on the committee of many international conferences, including IRPS, IEDM, SSDM, Symposium on VLSI Tech., and so on. He is an IEEE Fellow, and a Fellow of the Japan Society of Applied Physics (JSAP).



Prof. Wood-Hi Cheng, IEEE Fellow

  • National Chung Hsing University, Taiwan

  • Title: The Art and Science of Packaging High-Coupling Photonics Devices and Modules

  • Abstract
  • Biography
    Wood-Hi Cheng is a Professor at National Chung Hsing University, Taiwan. He received the Ph.D. degree in physics from Oklahoma State University, Stillwater, in 1978. He was the Director of the Institute of Electro-Optical Engineering (1994-2000), Dean of College Engineering (2002-2005), and the Chair of the Southern Taiwan Opto-Electronics Center of Excellence (2007-2011) from the National Sun Yat-sen University. He was a Program Director of Optoelectronics in the National Science Council (2009-2011) of Taiwan providing research grants and direction. Professor Cheng’s research and development is contributions to photonic package technology, including high-speed laser module packaging, high-coupling devices and modules packaging employing automated process, passively mode-locked fiber lasers employing carbon nanotubes or graphene, high-reliability glass-doped phosphor-converted high-power white-light-emitting diodes, and 300-nm ultrabroadband Cr-doped fiber amplifiers. Prof. Cheng’s most significant R&D is the demonstration of record ultra-broadband 300-nm Cr-doped fibers (CDFs). The CDFs have been used for the first time as a broadband Cr-doped fiber amplifier (CDFA) for use in a 40-Gb/s error-floor free data fiber-optic transmission. Prof. Cheng is a Fellow of IEEE, OSA, and SPIE. He served as a Chair for the IEEE Photonics Society, Taipei Chapter, during 1999–2000, and served as a Chair for the OSA, Taipei Chapter during 2005–2006. He was recipient of the IEEE Photonics Engineering Achievement Award in 2010 for his contributions to design, development and commercialization compact solid-state laser modules, and the 2011-2013 IEEE Photonics Society Distinguished Lecturer Award.


Prof. Juin J. Liou IEEE Fellow

  • University of Central Florida, US

  • Title: "Prospect and Outlook of Electrostatic Discharge (ESD) Protection in Emerging Technologies"

  • Abstract
    Electrostatic discharge (ESD) is one of the most prevalent threats to electronic components. It is an event in which a finite amount of charge is transferred from one object (i.e., human body) to the other (i.e., microchip). This process can result in a very high current passing through the microchip within a very short period of time, and hence more than 35% of chip damages can be attributed to the ESD event. As such, designing on-chip ESD structures to protect integrated circuits against the ESD stress is a high priority in the semiconductor industry. The continuing advancement in semiconductor technology makes the ESD-induced failures even more prominent. In fact, many semiconductor companies worldwide are having difficulties in meeting the increasingly stringent ESD protection requirements for various electronics applications, and one can predict with certainty that the availability of effective and robust ESD protection solutions will become a critical and essential component to the well-being and commercialization of next-generation electronics. An overview on the ESD sources, models, protection schemes, and testing will first be given in this talk. This is followed by the exploration and evaluation of ESD protection solutions in emerging Si nanowire, organic, and GaN technologies. Challenges and difficulties associated with the ESD design and optimization for these technologies will be addressed.
  • Biography
    Juin J. Liou received the B.S. (honors), M.S., and Ph.D. degrees in electrical engineering from the University of Florida, Gainesville, in 1982, 1983, and 1987, respectively. In 1987, he joined the Department of Electrical and Computer Engineering at the University of Central Florida (UCF), Orlando, Florida where he is now the UCF Pegasus Distinguished Professor and Lockheed Martin St. Laurent Professor of Engineering. His current research interests are Micro/nanoelectronics computer-aided design, RF device modeling and simulation, and electrostatic discharge (ESD) protection design and simulation. Dr. Liou holds 8 U.S. patents (4 more filed and pending), and has published 10 books (3 more under preparation), more than 270 journal papers (including 18 invited review articles), and more than 220 papers (including more than 90 keynote and invited papers) in international and national conference proceedings. He has been awarded more than $14.0 million of research contracts and grants from federal agencies (i.e., NSF, DARPA, Navy, Air Force, NASA, NIST), state government, and industry (i.e., Semiconductor Research Corp., Intel Corp., Intersil Corp., Lucent Technologies, Alcatel Space, Conexant Systems, Texas Instruments, Fairchild Semiconductor, National Semiconductor, Analog Devices, Maxim Integrated Systems, Allegro Microsystems, RF Micro Device, Lockheed Martin), and has held consulting positions with research laboratories and companies in the United States, China, Japan, Taiwan, and Singapore. In addition, Dr. Liou has served as a technical reviewer for various journals and publishers, general chair or technical program chair for a large number of international conferences, regional editor (in USA, Canada and South America) of the Microelectronics Reliability journal, and guest editor of 7 special issues in the IEEE Journal of Emerging and Selected Topics in Circuits and Systems, Microelectronics Reliability, Solid-State Electronics, World Scientific Journal, and International Journal of Antennas and Propagation. Dr. Liou received ten different awards on excellence in teaching and research from the University of Central Florida (UCF) and six different awards from the IEEE. Among them, he was awarded the UCF Pegasus Distinguished Professor (2009) – the highest honor bestowed to a faculty member at UCF, UCF Distinguished Researcher Award (four times: 1992, 1998, 2002, 2009) – the most of any faculty in the history of UCF, UCF Research Incentive Award (three times: 2000, 2005, 2010), UCF Trustee Chair Professor (2002), IEEE Joseph M. Biedenbach Outstanding Engineering Educator Award in 2004 for his exemplary teaching, research, and international collaboration, and IEEE Electron Devices Society Education Award in 2014 for promoting and inspiring global education and learning in the field of electron devices. His other honors are Fellow of IEEE, Fellow of IET, Fellow of Singapore Institute of Manufacturing Technology, Fellow of UCF-Analog Devices, Distinguished Lecturer of IEEE Electron Device Society (EDS), and Distinguished Lecturer of National Science Council. He holds several honorary professorships, including the Chang Jiang Scholar Endowed Professor of Ministry of Education, China – the highest honorary professorship in China, NSVL Distinguished Professor of National Semiconductor Corp., USA, International Honorary Chair Professor of National Taipei University of Technology, Taiwan, Chang Gung Endowed Professor of Chang Gung University, Taiwan, Feng Chia Chair Professor of Feng Chia University, Taiwan, Chunhui Eminent Scholar of Peking University, China, Cao Guang-Biao Endowed Professor of Zhejiang University, China, Honorary Professor of Xidian University, China, Consultant Professor of Huazhong University of Science and Technology, China, and Courtesy Professor of Shanghai Jiao Tong University, China. Dr. Liou was a recipient of U.S. Air Force Fellowship Award and National University Singapore Fellowship Award. Dr. Liou has served as the IEEE EDS Vice-President of Regions/Chapters, IEEE EDS Treasurer, IEEE EDS Finance Committee Chair, Member of IEEE EDS Board of Governors, and Member of IEEE EDS Educational Activities Committee.


Prof. Fu-Liang Yang

  • Distinguished Research Fellow
    Research Center for Applied Sciences, Academia Sinica, Taiwan

  • Title: Next Generation Blood Test Electronics for Home-Based Health Care

  • Abstract
    Point-of-care diagnosis, especially in-house self-operating detection, has attracted significantly increasing attentions, simply due to it could be a solution to alleviate the heavy health-care resource shortage for inevitable aging society. However, so far there are very few successful medical devices could play the role, excepting blood glucose and pressure monitor. The major obstacle is mainly attributed to conventional well-established in-vitro-diagnostics (IVD) in clinical units requiring big system and being too complicated to be operated by patients in house. Very recently, great advance with technologies of micro-lab on a chip may cover the unmet medical demands. Versatile one-touch "multi-function" hand-held devices with prototypes will be commercialized soon. In this paper we will summaries our experiences on varied microfluidic or electronic devices for rapid identification of infectious disease (T. B. and influenza), cancer biomarkers, and other pathogens of bacteremia and sepsis in human blood. Relevant nano technologies will be addressed, including blood sample separation, concentration of target species, and high sensitivity biosensors of Surface-Enhanced Raman Spectroscopy, Surface Plasmon Resonance, and advanced microbalance, and their surface modification and surface analysis. Test paper type detections will also be presented. Finally, our perspectives for emerging non-invasive-diagnosis electronics to monitor blood dynamic phenomena will be discussed, such as heart rate, relax behaviors, sPO2, blood glucose, blood pressure, etc.
  • Biography
        Fu-Liang Yang received the B.S. degree in materials science and engineering from the National Tsing Hua University, Taiwan, R.O.C., in 1989, and the Ph.D. degree in materials science and metallurgy from the University of Cambridge, U.K., in 1994. From 1994 to 2000, Dr. Yang was with Vanguard International Semiconductor Corporation (VIS), where he worked on DRAM process and device development. He joined TSMC in 2000 as a Device Technical Section Manager. From 2002 to 2006, he managed an exploratory department for developing novel transistor architecture and process technologies of sub-32nm node logic (FinFET and SOI) and nonvolatile memories. He was elected as an TSMC Academician, TSMC Academy, in 2004. From January 2007 to July 2008, he has conducted a phase-change memory program for NAND/NOR Flash replacement in TSMC. He has been appointed as Director General of National Nano Device Laboratories, Taiwan, from August 2008 to April 2013. Then he has been engaged with Academia Sinica, Taiwan, as Director of Patent Transfer Office and Distinguished Research Fellow of Research Center for Applied Sciences.

        Dr. Yang has conducted more than 40 IEDM and VLSI Symposium papers, and several invited talks at international conferences. He has also invented or co-invented more than 240 patents for advanced CMOS devices and dynamic/static/nonvolatile memory technologies. He has demonstrated CMOS scaling to record gate length of 5nm in 2004, achieved functional resistance memory cell array with half pitch down to record 9nm in 2010, and also conducted the first 16nm and 10nm functional SRAM cell in 2009 and 2013, respectively. He was a technical subcommittee member of IEDM 2010-2011, a program subommittee member and vice chair of SSDM 2010-2015, and also an international reviewer of Singapore National Advance Memory Program, SERC 2009 and 2011.

        Since 2008, Dr. Yang has also extended his research focus from CMOS device scaling to integrated bio-medical sensor systems. His laboratory and collaboration partners includes medical doctors, bio-chemistry scientists, and even wire-less communication experts. He was awarded “National Innovation Award” in 2012 for“A Label-Free Method for the Rapid Identification of Rare-Pathogens from Human Blood” by Institute for Biotechnology and Medicine Industry.






The 4th International Symposium on Next-Generation Electronics